1. Field of the Invention
The present invention relates to an isolation layer in a semiconductor device. More particularly, the present invention relates to a shallow trench isolation (STI) layer in a semiconductor device.
2. Description of the Related Art
With the development of better semiconductor manufacturing techniques, significant progress has been made in increasing the speed and the degree of integration of semiconductor devices. In achieving these improvements, higher density patterns and smaller sizes have become increasingly more important and, in many cases, required. For example, wide isolation regions in semiconductor devices have these requirements of higher density patterns and smaller sizes.
Local oxidation of silicon (LOCOS) layers have been mainly used as conventional isolation layers of semiconductor devices. However, bird""s beak configurations are created at the edges of the isolation layer formed by the LOCOS method and thus the area of active regions is reduced and current leakage occurs. Currently, STI layers having narrow widths and excellent isolation characteristics are widely used.
A cross-sectional view describing a formation method of a conventional STI layer in semiconductor devices is shown in FIG. 1. Referring to FIG. 1, a blocking pattern (not shown) is formed on a semiconductor substrate 10 to expose an isolation region. The semiconductor substrate 10 has a cell area, a core area and a peripheral area. The blocking pattern may consist of a stack of an oxide layer and a silicon nitride layer. The exposed semiconductor substrate 10 is etched to a predetermined depth using the blocking pattern as a mask to form trenches t1 and t2. The trench t1 may be formed in the cell area and the trench t2 may be formed in the core and peripheral areas. The process used for forming the trenches t1 and t2 is a plasma dry etching method.
The dry etching process for forming the trenches t1 and t2 may cause silicon lattice damage on the inner surfaces of the trenches t1 and t2. Conventionally, to reduce such silicon lattice damage, a sidewall oxide layer 12 is formed by thermally oxidizing the inner surfaces of the trenches t1 and t2. The sidewall oxide layer 12 is a thin layer of about 50-100 xc3x85. Also, the formation of the sidewall oxide layer 12 removes points generated at corners PP of the trenches t1 and t2.
Subsequently, a silicon nitride liner 14 is formed on the surface of the sidewall oxide layer 12. As the sidewall of the trench is oxidized by an additional thermal oxidation after an isolation process, the sidewall oxide layer bulks up. The silicon nitride liner 14, as known, blocks oxidation and prevents the generation of defects on the substrate due to the bulk increase in the sidewall oxide layer.
A dielectric material, for example, a high-density plasma (HDP) dielectric layer is deposited over the resultant semiconductor substrate 10 to completely fill the trenches t1 and t2. Next, a chemical mechanical polishing (CMP) process is performed on the HDP dielectric layer and the blocking pattern until the surface of the semiconductor substrate 10 is exposed. Additionally, trenches t1 and t2 are filled with the HDP dielectric layer. This completes the formation of an STI layer 16.
However, forming the thin and uniform sidewall oxide layer 12 causes the following problems. With reference to FIGS. 2A and 2B, since hot carriers of a highly integrated semiconductor metal-oxide-semiconductor (MOS) transistor generally have high energy, they enter into a thin gate oxide layer 22 or easily penetrate through the sidewall oxide layer 12 into the STI layer 16. The hot carriers penetrating into the STI layer 16 are mainly negative charges, namely, electrons 30, which are easily trapped in the silicon nitride liner 14 of the STI layer 16 and at the interface between the silicon nitride liner 14 and the sidewall oxide layer 12. The electrons 30 are closely trapped since the sidewall oxide layer 12 is very thin as described above. In the case where there are electrons 30 at the edge of the STI layer 16, positive charges, namely, holes are induced in the semiconductor substrate 10 (on which MOS transistors are formed) at the circumference of the STI layer 16. Since the electrons 30 are trapped in the silicon nitride liner 14 and on the interface between the silicon nitride liner 14 and the sidewall oxide layer 12, the holes 32 in the semiconductor substrate 10 are gathered closely together.
As shown in FIG. 2A, since the majority carriers in an N-channel field effect transistor (N-FET) are the electrons 30, a path is not formed between n-type junction areas 26a and 26b, in which the electrons 30 function as majority carriers, even though the holes 32 are densely induced at the circumference of the STI layer 16.
Meanwhile, as is well known in the art, since the majority carriers in a P-channel field effect transistor (P-FET) are the holes 32, as shown in FIG. 2B, the holes 32, which are arranged densely at the circumference of the STI layer 16, function as a current path xe2x80x9cIxe2x80x9d connecting p-type junction areas 28a and 28b isolated by the STI layer 16. Consequently, due to the current path 1, although p-type junction areas 28a and 28b are isolated by the STI layer 16, leakage current, such as abnormally increased standby current, is generated between adjacent P-FETs, thereby deteriorating the characteristics of the P-FETs. Here, reference numeral 24 denotes a gate electrode of a MOSFET.
Furthermore, in the case where a P-FET (not shown) is on the interface between the STI layer 16 and an active region, a channel area of the P-FET abuts the silicon nitride liner 14 where the electrons are trapped by the thin sidewall oxide layer 12. Consequently, the electrons trapped in the silicon nitride liner 14 easily induce holes in the channel area of the P-FET in the interface. Also, the holes induced in turning on the P-FET are not easily removed and remain when turning off the P-FET. Thus, the length of the channel of the P-FET on the interface is gradually reduced thereby changing the threshold voltage and breakdown voltage. Consequently, the characteristics of the P-FET are altered.
To solve the above problems, it is a feature of an embodiment of the present invention to provide a method of forming a shallow trench isolation (STI) in a semiconductor device, which is capable of reducing leakage current between P-FETs and ensuring proper characteristics of the P-FETs.
Accordingly, to achieve this feature, there is provided a method of forming a shallow trench isolation layer in a semiconductor device. In this method, a first trench and a second trench are formed in an area selected from a semiconductor substrate. A sidewall oxide layer is formed on the inner surfaces of the first and second trenches. An anti-oxidation liner is formed on the surface of the sidewall oxide layer. A mask layer is formed on the semiconductor substrate surface including the anti-oxidation liner. A photoresist pattern is formed to expose the mask layer in the second trench. The mask layer is patterned in the form of the photoresist pattern. The photoresist pattern is then removed. The anti-oxidation liner is etched in the form of the mask layer. A dielectric material is formed to completely fill the first and second trenches. A shallow trench isolation layer is formed by chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and is other circuit devices and the second trench provides isolation between P-FETs.
The first trench may be formed in the cell area and the second trench may be formed in the core and peripheral areas.
The sidewall oxide layer may be formed by a thermal oxidation method. The anti-oxidation liner may be formed of a silicon nitride layer or a silicon oxynitride layer and may be etched by a 150xc2x0 C. phosphoric acid solution. The mask layer is a dielectric layer having a better etch selectivity ratio against a 150xc2x0 C. phosphoric acid solution than the anti-oxidation liner. The mask layer may be a silicon oxide layer. The dielectric material filling the first and second trenches may be a high-density plasma (HDP) dielectric layer or a tetraethyl orthosilicate. oxide (TEOS) layer.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.